Field of the Invention
The present invention relates to a semiconductor test apparatus, and for example, relates to a semiconductor test apparatus controlling a tester to which a plurality of devices are connected.
Description of the Background Art
A semiconductor test apparatus testing a semiconductor device has conventionally been known,
For example, in a semiconductor test apparatus according to Japanese Patent Laying-Open No 2004-144488, a pattern feature extraction unit (2) extracts a feature of a test pattern and a pattern conversion unit (3) sorts test patterns in consideration of features of extracted test patterns and outputs the test patterns together with a scrambling code A pattern memory control unit (5) accesses a pattern memory (4), reads the test pattern converted by the pattern conversion unit (3), and transfers only a unit of which transfer is required to a tester control unit (6) The tester control unit (6) reconstitutes the read test pattern based on the scrambling code, generates a test waveform and applies the waveform to a tested LSI, and determines whether or not the tested LSI is good.